22nm後英特爾FinFET可能需要使用SOI
上網時間: 2012年06月12日
根據工程顧問公司 Chipworks 日前披露的英特爾(Intel) 22nm FinFET 元件剖面圖，以及EDA公司 Gold Standard Simulations (GSS) 針對該元件所做的多種電氣特性建模結果，顯示出了這個最新 22nm FinFET 的物理變異特性。
GSS 公司CEO Asen Asenov 得出的結論是：在22nm之後，英特爾或許必須為其FinFET採用絕緣層上覆矽(SOI)晶圓。這或許也將對準備在晶片製程中導入FinFET技術的晶圓廠帶來啟示。
GSS 已經進行了一些FinFET的TCAD模擬，並在其部落格上探討英特爾的22nm FinFET元件剖面圖實際上是更接近三角形的梯形，而非矩形。
而這次，GSS比較了不同形狀FinFET元件的導通電流(on-current)。GSS指出，在邏輯應用中，多個鰭是並聯連接的，這使其具備非常平均的特性，但在SRAM電路中，單一鰭的變化則成為了特性和性能限制的關鍵。
三個以Garand模擬域覆蓋的英特爾FinFET元件TEM影像。 / 資料來源：GSS公司
GSS表示，儘管三個FinFET元件的鰭外形存在著顯著差異，但導通電流的差距都在4%以內。
“與整片晶圓上所有晶片的製程變異相比，4%的變化算是很微小的。但這仍然是額外的變異，”Asenov說。他進一步指出，模擬結果顯示，FinFET製造技術是高度複雜且難以實現的，部份原因是缺乏可在電晶體之間提升淺溝槽隔離氧化物的平面化製程。而這可能會導致塊狀FinFET的高度改變。
Asenov承認，他們必須用假設數字來進行模擬。他們假設這些鰭實際上是未摻雜的，但在鰭的下方卻具有一個穿透固定器(punch-through stopper)摻雜物區域。“我們並不知道摻雜情況(dopant profiles)和應力，但我們盡力做出合理的假設，”Asenov說。
導通電流、離子和閘極長度。 / 資料來源：GSS公司
GSS同時展示針對寬度為10nm和8nm的矩形FinFET元件模擬結果，並表示英特爾應該還會繼續微縮下去。“如果你可以製造出矩形的FinFET元件，你就能得到大約20%左右的性能改進。”
Asenov s指出，從塊狀FinFET轉移到在SOI上建構FinFET元件，有助於解決一些問題。“埋入式氧化層意味著不會再有填充溝槽的問題。而鰭高度則取決於氧化層上的矽元件深度。”
Asenov進一步指出，他認為塊狀FinFET很難再微縮到16nm或14nm。SOI將有助於推動FinFET朝16nm甚至11nm發展。當然，晶圓會更昂貴，但晶圓廠總會知道如何節省成本。
GSS和格拉斯哥大學(University of Glasgow)的研究人員曾在2011年的國際電子元件會議(IEDM)上發表在SOI上實現FinFET的論文，該論文同時探討了他們如何滿足11nm CMOS節點對更低變異性的要求。
編譯： Joy Teng
(參考原文： Intel FinFETs vary, may need SOI for shrink, says GSS ，by Peter Clarke)
Intel FinFETs vary, may need SOI for shrink, says GSS
Peter Clarke
6/6/2012 7:01 AM EDT
LONDON – Intel's 22-nm FinFETs show physical variability according to cross-sectional photographs from engineering consultancy Chipworks Inc. (Ottawa, Ontario) and EDA company Gold Standard Simulations Ltd. (GSS) has attempted to model electrical characteristics of various examples.
One conclusion drawn by Professor Asen Asenov, CEO of GSS (Glasgow, Scotland), is that Intel may need to turn to silicon-on-insulator wafers to scale its FinFETs below 22-nm. This may also have implications for foundries which are yet to introduce FinFET technology into their chip manufacturing processes.
GSS has already done some TCAD simulation of FinFETs and posted findings in a blog that discussed the fact that at 22-nm Intel's FinFETs are trapezoidal rather than rectangular in cross-section (see Intel's FinFETs are less fin and more triangle).
The latest GSS blog seeks to compare the on-current of differently-shaped FinFETs. It points out that in logic applications multiple fins are connected in parallel, resulting in an averaging of their characteristics, but in SRAM circuits the variability of a single fin is a key characteristic and performance limiter.
TEM images of three Intel FinFETs with the GARAND simulation domain overlaid. Source: GSS
The characteristic dimensions of three FinFETs were fed into the GSS Garand simulator and it revealed that at 22-nm, nature appears to have worked to Intel's advantage. "Despite significant differences in the shape of the three fins, the difference in the on-current is within a 4 percent range," the blog states.
"Compared with process variation across the chip or across the wafer 4 percent is small. But it is additional variation," Professor Asenov told EE Times. He added that the simulation revealed that the FinFET process technology is complex and difficult to implement, partly because of the lack of a planarization process that can level-up shallow trench isolation oxides between transistors. One result of this is that bulk FinFET heights can vary, he said.
Professor Asenov admitted that a number of assumptions have to be made to allow the simulations to run. It is assumed that the fin itself is virtually undoped but there is a punch-through stopper dopant region beneath the fin. "We don't know about dopant profiles and strain, but we have tried to make favorable assumptions," said Professor Asenov.
Click on image to enlarge.
Dependence of on-current, ION, on gate length. Source: GSS
GSS has included results for simulations of rectangular cross-section FinFETs with 10-nm and 8-nm widths hinting at where the company thinks Intel must go next. "If you can make them [FinFETs] rectangular you will gain significantly in terms of performance, about a 20 percent gain."
Professor Asenov said that moving from bulk FinFETs to FinFETs constructed on SOI wafers could solve a number of problems. "The buried oxide layer means you don't have the problem of filling trenches. The height of the fin is determined by the depth of the silicon above the oxide."
Professor Asenov added: "I think Intel just survived at 22-nm. I think bulk FinFETs will be difficult to scale to 16-nm or 14-nm. I think that SOI will help the task of scaling FinFETs to 16-nm and 11-nm. Of course, the wafers are more expensive, but you save money with less processing."
Researchers from GSS and the University of Glasgow published a paper at the International Electron Devices Meeting of 2011 that dealt with FinFETs implemented in SOI wafers and how they could meet the low statistical variability requirements of 11-nm CMOS.
