TSMC Is Working on 16nm FinFET This Year, And On 10nm Chips for 2015
TSMC plans to outrace Global Foundries and Samsung to 16nm FinFET chips, and they expect to have them in silicon by the end of the year. Don’t get too excited yet, though, as that still means we’re at least another year and a half away on top of that, until we actually see devices with 16nm FinFET chips, and we still have to see the 20nm chips first, at which the next-gen Krait, Cortex A15, and perhaps even Tegra 5 will be made.
Nvidia also promised Tegra 6 will be made at 16nm FinFET (they are TSMC customer), but we won’t see that until 2016. TSMC also has plans for 10nm chips, and utilizing EUV (extreme ultra-violet) litography, but that seems to pose some challenges for now, so they are also researching e-beams in parallel. TSMC founder believers Moore’s Law should last us at least another 7-8 years:
“It looks like we have another 7 to 8 years ahead in advances — maybe more — we can see in technology down to 10 and even 7 nm,” said Morris Chang, founder and chief executive of TSMC, speaking to a small group of press after a keynote here.“Moore’s Law is going to go on and we will be there — if anyone pursues it, we will pursue it,” he told an audience of several hundred chip designers.
TSMC will have 20 tapeouts for its 20nm process this year (the regular kind, not the experimental 20nm FinFETprocess), and expects mass production for next year. According to them, a Cortex A57 chip at 20nm should be 40% faster than a Cortex A9 at 28nm, and at 16nm FinFET it should be 90% faster, all at the same clock speed.
If their EUV litography is ready for the 10nm process, they will get another 35% performance improvement over the 28nm Cortex A9, at the same power consumption, or a 40% increase in power consumption, at the same performance. What we’ll probably see is a compromise between the two, though.
What this increased competition between the foundries means, is that ARM chips will soon catch-up with Intel, at least on the mobile side. Intel’s Bay Trail Atom will be made at 22nm, and will be released at the end of the year, while next-gen ARM chips will be released at 20nm only a few months later (but the node is also slightly smaller, so a little ahead of Bay Trail). Plus, right now ARM chips like the Cortex A15 have significantly higher performance than Atom already, and the same ARM chips also tend to have much higher GPU performance.
TSMC, Global Foundries, and Samsung should become increasingly more dangerous competition, as their chips get to be made at around the same node and around the same time, and their ARM chips get higher and higher performance that is “good enough” for most people, while costing OEM’s much less than what Intel is charging, and with plenty of chip makers that OEM’s can select.
ARM, TSMC, Cadence produce first 16nm finfet Cortex processor
Friday 05 April 2013 00:14
ARM and Cadence have announced the first Cortex-A57 processor test chip fabricated on TSMC’s 16nm finfet manufacturing process technology.
According to the companies, this test chip resulted in several optimisations between manufacturing process, design IP, and design tools, which will be critical for production of 16nm chips.
“More than ever, success at the leading edge of innovation requires deep collaboration. When designing SoCs incorporating advanced processors, like the Cortex-A57, and optimizing the implementation using physical IP created for FinFET processes, the expertise of our partners is needed,” said Tom Cronk, general manager, processor division at ARM.
The 16nm process using finfet technology required new design methodologies. For example, the design flow tackled RC extraction for 3D transistors, complex resistance models for interconnect and vias, quantised cell libraries and double patterning across more layers.
The test chip was implemented using the complete Cadence RTL-to-signoff flow, Cadence Virtuoso custom design platform, ARM Artisan standard cell libraries and TSMC’s memory macros.
“This major milestone was challenging on all fronts, requiring engineers from ARM, Cadence and TSMC to work as a unified team,” said Dr. Chi-Ping Hsu, senior vice president of R&D for the Silicon Realization Group at Cadence.
According to the companies, this test chip resulted in several optimisations between manufacturing process, design IP, and design tools, which will be critical for production of 16nm chips.
“More than ever, success at the leading edge of innovation requires deep collaboration. When designing SoCs incorporating advanced processors, like the Cortex-A57, and optimizing the implementation using physical IP created for FinFET processes, the expertise of our partners is needed,” said Tom Cronk, general manager, processor division at ARM.
The 16nm process using finfet technology required new design methodologies. For example, the design flow tackled RC extraction for 3D transistors, complex resistance models for interconnect and vias, quantised cell libraries and double patterning across more layers.
The test chip was implemented using the complete Cadence RTL-to-signoff flow, Cadence Virtuoso custom design platform, ARM Artisan standard cell libraries and TSMC’s memory macros.
“This major milestone was challenging on all fronts, requiring engineers from ARM, Cadence and TSMC to work as a unified team,” said Dr. Chi-Ping Hsu, senior vice president of R&D for the Silicon Realization Group at Cadence.
ARM、台積電攜手16nm FinFET 打造Cortex-A57
‧數位資訊 2013/04/02
ARM宣佈將與台積電合作16nm FinFET製程技術，預計用於旗下Cortex-A57處理器產品設計，並且準備應用於包含高階電腦、平板與伺服器等高度運算需求產品。
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針對旗下高階Cortex-A57處理器產品設計，ARM宣佈將與台積電合作16nm FinFET製程技術，同時優化64位元ARMv8處理器系列產品。配合ARM Artisan實體IP、台積電記憶體巨集，以及台積電提供開放創新平台 (Open Innovation Platform,OIP)生態環境架構下的電子設計自動化 (Electronic Design Automation,EDA)技術，在半年內即完成從暫存器轉換階層 (RTL)到產品設計定案流程。
未來雙方將合力打造更優異、節能的Cortex-A57處理器，以及相關元件資料庫，並且推出以ARM技術為基礎的高效能系統單晶片 (SoC)，並且對應前期客戶在16nm FinFET製程技術上的設計實作。
至於在處理器效能表現方面，根據ARM說法將會是現行處理器規格的3倍以上 (在相同電力損耗下)，至於整體電力效能則估計會是5倍左右 (在相同運作時脈下)。
就先前說法，ARM所提出的big.LITTLE技術也經能用於Cortex-A53與Cortex-A57架構處理器，而近期更新旗下Tegra處理器發展藍圖的Nvidia，也預計在2015年後推出代號為「Parker」的Tegra處理器，屆時將採用ARM所提出64位元處理器設計，估計將會採用此項技術打造。
全文網址: ARM、台積電攜手16nm FinFET 打造Cortex-A57 | 通訊報導 | 通訊世界 | udn數位資訊 http://mag.udn.com/mag/digital/storypage.jsp?f_ART_ID=448738#ixzz2Qegtootw
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迎戰三星、英特爾 台積製程飆速
晶圓代工龍頭台積電本周四（18日）將召開法說會，上周於美國聖荷西（San Jose）舉辦的2013年技術論壇中，卻意外宣示包括16奈米鰭式場效電晶體（FinFET）、極紫外光（EUV）等新技術研發及投產進度全部往前拉。
業界認為，台積電將新技術投產進度時程全面提前，除了新技術研發有所突破外，另一戰略考量，即是為了迎戰聲勢如日中天的韓國三星，以及即將由薄紗後走到台前的英特爾。
今年是台積電傾全力拉高28奈米產能的一年，原本規劃明年才開始拉升20奈米產能，但20奈米量產時間點可望提前至今年底開始。台積電在竹科12吋廠Fab12、南科12吋廠Fab14，已有20個20奈米晶片完成設計定案（tape-out），且多數為新一代ARM Cortex A15處理器核心的晶片。業界人士指出，當中自然包括了蘋果下一代A7處理器。
台積電原本2015年後才真正進入16奈米FinFET世代，但現在已經確定今年底開始試產第一片16奈米FinFET製程晶圓，應是投產首顆64位元ARM Cortex-A57架構及ARMv8指令集設計晶片。
由此來看，明年台積電就會進入16奈米FinFET世代，比原本預期早了一年。台積電雖然與英特爾、三星等共同加入了微影設備大廠荷商艾司摩爾（ASML）的「客戶聯合投資專案」，但去年底時，仍認為EUV技術尚未成熟，16奈米及10奈米仍會用到多重曝光浸潤式（Multi-Patterning Immersion）微影技術，7奈米後才會進入EUV世代，約在2016~2017年。
不過，台積電指出，首片採用EUV微影投片的10奈米晶圓，可望在2015年底開始投產出貨。雖然台積電仍在評估電子束微影（e-beam）可行性，但由此來看，台積電EUV製程將提前1~2年時間進入生產階段。
台積電將20奈米SoC製程、16奈米FinFET製程、EUV微影製程等生產時程全面往前拉，原本預估今年90億美元資本支出顯然不足，外資分析師均認為，台積電今年資本支出拉高到100億美元已無可避免，明年可能還會拉高到100億美元以上，才能將先進製程投產時間點順利提前。
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