台積電28奈米大躍進

ＣＨＥＣＫ　ＰＯＩＮＴ　Ｒｅｆｅｒｅｎｃｅ

INTEL currently run at 32nm for cpu/chipset products (2011/Q1)

ＡＭＤ　ｃｕｒｒｅｎｔｌｙ　ａｔ　４０ｎｍ　ｆｏｒ　ｃｐｕ（２０１１／Ｑ１）

2011-02-21
工商時報
【記者張志榮╱台北報導】

    　台積電28奈米產能大躍進！日商大和證券亞洲科技產業研究部主管陳慧明指出，第一季每月出貨已可達5,000片，分別由Altera與Xilinx（各佔50％）吃下；此外，備受外資圈期待的蘋果A5 CPU訂單，也可望重回台積電懷抱。
    　花旗環球證券半導體分析師徐振志指出，台積電在28奈米打遍天下無敵手其實有跡可循，主要競爭對手IBM先前曾在一場論壇中表示，將從20奈米開始走gate last製程，這等於宣告28奈米gate first已走不下去，對客戶而言當然採用台積電的28奈米會比較安心。
    　陳慧明表示，目前市場對於28奈米的需求非常強勁，包括應用微處理器（AP）供應商、Nvidia（主要為Tegra 3）、德儀（主要為OMAP 5）、高通（主要為Snapdragon與APQ8064）等，都急著採用28奈米製程，這意味著ARM CPU供應商已加速在絕大多數高階製程的應用，影響所及，不但有助於蘋果A5 CPU重回台積電懷抱，也會對英特爾的CPU業務造成不小壓力。
    　不過，陳慧明指出，在2011年全球平板電腦出貨約5,000萬台的預估值下，ARM CPU對2011年台積電營收貢獻幅度仍然有限，可能不到3％。
    　較值得注意的是，陳慧明認為蘋果A5 CPU訂單可望重回台積電懷抱，先前A4所以不在台積電下單，主要是受12吋產能吃緊、蘋果給的價格較低及三星在3D IP較有利基所致。但在：一、台積電在28奈米製程遙遙領先；二、三星與蘋果在智慧型手機與平板電腦等有利益衝突；三、台積電在3D解決方案IP已開始追上來等因素考量下，蘋果A5 CPU重回台積電懷抱應該是可以預期的結果。

http://richard-rrb.blogspot.com/2010/04/blog-post_29.html
2010年4月30日星期五

台積電法說會摘要(口語版)

2Q10 guidance

營收: 1,000E~1,020E, +8.5~10.6%
GP%: 48~50%
OP%: 36.5~38.5%
依此推算:
UTR: 100%
Wafer shipments: 2,833K, +11% QoQ
ASP: US$1,087, +2% QoQ
但因為NT$/US$假設為31.3(1Q10 31.96)，所以營收只+10.5% QoQ

Moore’s Law

Moore’s Law至少還有10年，而10年之後如果Moore’s Law停止了，製程演進走到盡頭，TSMC還有另外10年的研發優勢，可以在將特定製程針對各種應用增加功能(features)，例如現在的先進製程是45/40nm(Intel的32nm)，但是各種特定的功能應用例如Embedded memory, CMOS image sensor, Analog, Mixed-mode, RF, MEMS, Power management, Display driver等等，製程都遠遠落後45/40nm，還是需要研發增加功能才能切入這些特定應用的市場。也就是說，TSMC的研發優勢至少還可以延續20年。

又例如，Morre’s Law變慢或停止了，但是system integration的趨勢還是會繼續進行，因此SoC就會從現在的System on die, 變成System in package(SIP)，TSMC必須要提供一個平台讓客戶可以繼續整合，因此切入(1)wafer level package, 從2D to 3D(立體封裝), (2)Silicon substrate等技術。

28nm技術時程

(1)28LP, low power, SiNO, Gate-First, 2010/6
(2)28HP, high performance, HKMG, Gate-Last, 2010/9
(3)28HPL, low power, HKMG, Gate-Last, End-2010
(4)28HPM, 希望兼顧high performance和low power，目標市場在於行動運算CPU，例如Smartphone or MID

Gate-Frist和Gate-Last之爭

針對Gate-First和Gate-Last之爭，目前選擇Gate-Last的只有TSMC和Intel，IBM陣營包括Samsumg, Global foundry, Chartered和一些IDM廠則選擇Gate-First，IBM陣營宣稱Gate-First做出來的die size比較小，製程上也有成本優勢，而且研發比較容易成功，但也承認比較適合low power, performance應用比較差，而蔣尚義認為，Gate-Last的製程步驟(process steps, 將影響cycle time, 而cycle time將影響成本)、和光罩層數(mask level)都和Gate-First類似，因此成本不會比較高，至於影響die size的design rule，和gate-first/gate-last無關，因此Gate-Last的die size也不會比較大，但是比較難做是真的，如果你學會的話，performance比較好，也不會比較貴。

蔣尚義大膽預測，Gate-Last終必成功，到了22/20nm，IBM陣營的對手們將全部轉回來做Gate-Last，將可證明他們選擇錯誤，蔣先生似乎暗示，對手陣營中，很快就會有人率先開始重新研發28nm的Gate-Last。

如果蔣先生所言不虛，則表示Globalfoundries和Chartered用Gate-First做需要hign performance的CPU，會比TSMC的Gate-Last差，那麼，AMD(PC)、IBM的CPU(Game)，可能就會有大問題了，AMD採用Bulk CMOS的CPU是否也被迫要轉單到TSMC? 未來一大堆ARM-based或MIPS-based的RISC CPU，是不是也都必須到TSMC投片?

RRB(Richard's Research Blog)查了一下Globalfoundries的網站，有這麼一段話:
The "Gate Last" approach to HKMG is costly and requires a number of additional processing steps. GLOBALFOUNDRIES has chosen to implement a "Gate First" approach because it is simpler and more scalable to future generations. The process flow is very similar to what was used for previous technology generations. The "Gate First" maximizes power efficiency and transistor scaling while minimizing die size and design complexity when compared to the alternative "Gate Last" approach.
http://www.globalfoundries.com/technology/tech_elements.aspx

很明顯的，Globalfoundries的說法和TSMC的說法剛好相反，事實只有一個，不是有人說謊，就是有人功力不夠，看得不透徹，以至於選錯技術路線，當然，RRB相信TSMC，畢竟，蔣先生當年在0.13um天險的銅製程Black Diamond和SILK之爭，曾經大敗IBM和U聯軍，讓TSMC在0.13um世代之後取得絕對的技術領先優勢，兩年多前張先生把已半退休的蔣先生找回來重新掌管RD，會不會再度大敗IBM聯軍，我們拭目以待。

這個議題對未來兩年foundry的競爭，甚至半導體業的競爭，應該都非常重要，很奇怪好像很少人關心這件事，大部份報告和媒體都沒有提。

2 意見:

匿名提到...

what I think is same with you. Due to Intel is alwaye the process tech leader (not tsmc), so if Intel think gate last is better; I do believe they are right. Just gate last cost should be little higher than gate first (more process). leonchang123@yahoo.com.tw

2010年8月18日下午7:27

Richard's Research Blog 提到...

Thnaks for your comments

2010年8月18日下午8:28

IEDM 2009: HKMG gate-first vs gate-last options

Speaking at the International Electron Devices Meeting (IEDM) in Baltimore, IMEC's Thomas Hoffman outlined challenges and possible options of high-k metal-gate (HKMG) transistor stack materials and processes for future device generations. He compared gate-first and gate-last advantages and disadvantages, the role of HKMG in advanced 3D transistor structures, such as the FinFET our tri-gate transistor, possible options to fix flatband roll-off problems, and an intriguing solution involving channel engineering with silicon germanium (SiGe). Hoffman provided his analysis during a short course session on Sunday. Hoffman said that what had become the standard material for the transistor gate dielectric -- silicon oxynitride (SiON) – ran out of steam at the 90nm node. Films could not be made much thinner than 11-12Å without creating excessive leakage current. The alternative is a high-k dielectric, such as HfO₂, which can reduce gate leakage by orders of magnitude. "With this new material we are able to sustain Moore's Law," Hoffman said. "It not only fixes the leakage problem but allows scaling to continue." Due to compatibility issues with standard polysilicon gates revolving around defects that cause "Fermi pinning" which prevents transistors from switching properly at low threshold voltages, high-k gate dielectrics must be paired with a metal gate electrode. "These defects in the bandgap prevent gate voltage swing. The end result is a high V_t," Hoffman said. An added advantage of metal gates is that a common reliability problem -- polysilicon depletion -- is suppressed. High-k has many challenging material requirements, particularly with thermal stability, morphology and interface quality, Hoffman noted -- thermal stability is typically poor, and films can be deposited with an amorphous morphology but then crystallize at higher temperatures. The conformality and topography of the deposition method are also critical, especially "as we move to 3D devices such as the FinFET," he said. Hafnium silicates provide "slightly better thermal stability" than HfO₂, he said, but at the expense of a lower k value. Nitrided hafnium silicates are a good compromise, he noted, and they could probably be used for the next device generation. Hf-Al-O offers a wide range of k-values, but needs more work to be put into production. The secret in successfully implementing HKMG, Hoffman said, is in finding a way to tune the threshold voltage (V_t) for both PMOS and NMOS transistors: "that's where things start to get complicated." One way is through capping layers in between the high-k and metal or between an interlevel dielectric (which sits atop the channel region) and the high-k material. Al₂O₃ and La₂O₃ are example of capping layer materials that have been extensively reported. Hoffman said that with the Al₂O₃ process, which is thermally activated, "you can form dipoles which set the desired workfunction."

High-k first, gate-last structure. (Source: Hoffman/IMEC, IEDM 2009; acknowledgement C. Auth, VLSI '08)

Another approach to V_t tuning is to select an electrode material with the desired work function. Many candidate materials with different work functions have been proposed and researched, but Hoffman said "there doesn't seem to be much consolidation." Candidates include TaN, TiN and TaSiN, some films with "richer" mixtures of Ta or N. One reason there has not been consolidation is that most metals tend to migrate towards midgap work functions after high-temperature anneals. For this approach to work then, it's important for metal to not be exposed to high temperatures, and the only way to do that is with a gate-last process strategy (sometimes called gate replacement or "cold flow" process). In a gate-last process, the high-k material is deposited dummy gates are created, followed by source/drain formation and an interlevel dielectric (ILD) deposition and polish. The dummy gates are removed and different workfuction metals are deposited for NMOS and PMOS. Companies that have reported on a gate-first process include IBM, UMC, Panasonic, Renesas, while gate-last processes have been reported by Intel and TSMC. Hoffman said a third approach, full silicidation (FUSI), where a polysilicon gate is totally converted to a silicide, has been abandoned due to a too-narrow process window. An interesting alternative described by Hoffman that achieves high V_t with scaled effective oxide thickness for PMOS is channel engineering. He said a SiGe channel process would allow gate-first process strategy, and would require only one capping layer instead of two. An on-going problem with HKMG, first reported by SEMATECH, is flat-band voltage roll-off. "As the flat-band voltage is rolling off, the PMOS Vt is going up again," Hoffman said. This problem is caused by oxygen vacancies/defects in the high-k material, which can diffuse and interlayer growth. There are two approaches to solving this problem, he noted. Since it's a thermally activated issue, going to lower or neutral thermal budgets would help. This might mean going from a spike anneal, for example, to a laser anneal. The second solution is to passivate by oxygenation, either lateral oxygenation after source/drain activation, or oxygenation through a thin layer of TiN (Hoffman referenced work by Cartier, from VLSI '09 and APL, vol. 95, 2009). Hoffman said that nobody has disclosed anything yet for the 22nm node, although he said that HKMG would have a role for 3D types of devices such as the FinFET. ＣＨＥＣＫＰＯＩＮＴ INTEL currently run at 32nm for cpu/chipset products (2011/Q1) ＡＭＤ　ｃｕｒｒｅｎｔｌｙ　ａｔ　４０ｎｍ　ｆｏｒ　ｃｐｕ（２０１１／Ｑ１） http://en.wikipedia.org/wiki/Intel_Core

Intel Core processor family
Brand	Desktop				Laptop
Brand	Code-named	Cores	Fab	Date released	Code-named	Cores	Fab	Date released
Core Solo	Desktop version not available				Yonah	1	65 nm	Jan 2006
Core Duo	Desktop version not available				Yonah	2	65 nm	Jan 2006
Core 2 Solo	Desktop version not available				Merom-L Penryn-3M	1 1	65 nm 45 nm	Sep 2007 May 2008
Core 2 Duo	Conroe Allendale Wolfdale	2 2 2	65 nm 65 nm 45 nm	Aug 2006 Jan 2007 Jan 2008	Merom Penryn	2 2	65 nm 45 nm	Jul 2006 Jan 2008
Core 2 Quad	Kentsfield Yorkfield	4 4	65 nm 45 nm	Jan 2007 Mar 2008	Penryn	4	45 nm	Aug 2008
Core 2 Extreme	Conroe XE Kentsfield XE Yorkfield XE	2 4 4	65 nm 65 nm 45 nm	Jul 2006 Nov 2006 Nov 2007	Merom XE Penryn XE Penryn XE	2 2 4	65 nm 45 nm 45 nm	Jul 2007 Jan 2008 Aug 2008
Core i3	Clarkdale Sandy Bridge	2 2	32 nm 32 nm	Jan 2010 Feb 2011	Arrandale Sandy Bridge	2 2	32 nm 32 nm	Jan 2010 Feb 2011
Core i5	Lynnfield Clarkdale Sandy Bridge Sandy Bridge	4 2 4 2	45 nm 32 nm 32 nm 32 nm	Sep 2009 Jan 2010 Jan 2011 Feb 2011	Arrandale Sandy Bridge	2 2	32 nm 32 nm	Jan 2010 Feb 2011
Core i7	Bloomfield Lynnfield Gulftown Sandy Bridge	4 4 6 4	45 nm 45 nm 32 nm 32 nm	Nov 2008 Sep 2009 Jul 2010 Jan 2011	Clarksfield Arrandale Sandy Bridge Sandy Bridge	4 2 4 2	45 nm 32 nm 32 nm 32 nm	Sep 2009 Jan 2010 Jan 2011 Feb 2011
Core i7 Extreme Edition	Bloomfield Gulftown	4 4	45 nm 32 nm 32 nm	Nov 2008 March 2010	Clarksfield Sandy Bridge	4 4	45 nm 32 nm	Sep. 2009 Jan 2011

http://en.wikipedia.org/wiki/List_of_Intel_chipsets

Chipset	Code Name	sSpec Number	Part numbers	Release Date	CPU socket	Bus Interface	Bus Speed	PCI Expresslanes	PCI	SATA	USB	FDI support	TDP
X58¹	Tylersburg	SLGBT (B2), SLGMX (B3), SLH3M (C2)	AC82X58 (IOH)	Nov 2008	LGA1366	QPI	Up to 25.6 GB/s	36 PCI-E 2.0 at 5 Gb/s	Yes	3 Gbit/s, 6 Ports	Rev 2.0, 12 Ports	No	28.6W²
P55	Ibex Peak	SLH24 (B3), SLGWV (B2)	BD82P55 (PCH)	Sep 2009	LGA1156	DMI	2 GB/s	8 PCI-E 2.0 at 2.5 Gb/s	Yes	3 Gbit/s, 6 Ports	Rev 2.0, 14 Ports	No	4.7W
H55	Ibex Peak	SLGZX(B3)	BD82H55 (PCH)	Jan 2010	LGA1156	DMI	2 GB/s	6 PCI-E 2.0 at 2.5 Gb/s	Yes	3 Gbit/s, 6 Ports	Rev 2.0, 12 Ports	Yes	5.2W
H57	Ibex Peak	SLGZL(B3)	BD82H57 (PCH)	Jan 2010	LGA1156	DMI	2 GB/s	8 PCI-E 2.0 at 2.5 Gb/s	Yes	3 Gbit/s, 6 Ports	Rev 2.0, 14 Ports	Yes	5.2W
Q57	Ibex Peak	SLGZW(B3)	BD82Q57 (PCH)	Jan 2010	LGA1156	DMI	2 GB/s	8 PCI-E 2.0 at 2.5 Gb/s	Yes	3 Gbit/s, 6 Ports	Rev 2.0, 14 Ports	Yes	5.1W
P67	Cougar Point	SLH84(B2) (Recalled) SLJ4C (B3)	BD82P67 (PCH)	January 9, 2011	LGA1155	DMI 2.0	4 GB/s	8 PCI-E 2.0	No	6 Gbit/s, 2 Ports & 3 Gbit/s, 4 Ports	Rev 2.0, 14 Ports	No	6.1 W
H67	Cougar Point	SLH82(B2) (Recalled) SLJ49 (B3)	BD82H67 (PCH)	January 9, 2011	LGA1155	DMI 2.0	4 GB/s	8 PCI-E 2.0	No	6 Gbit/s, 2 Ports & 3 Gbit/s, 4 Ports	Rev 2.0, 14 Ports	Yes	6.1 W
Z68	Cougar Point	SLHAT(B2) SLJ4F(B3)	BD82Z68 (PCH)	2nd Quarter, 2011	LGA1155	DMI 2.0	4 GB/s	8 PCI-E 2.0	No	6 Gbit/s, 2 Ports & 3 Gbit/s, 4 Ports	Rev 2.0, 14 Ports	Yes	6.1 W
H61	Cougar Point	SLH83(B2) SLJ4B(B3)	BD82H61 (PCH)		LGA1155	DMI 2.0	4 GB/s	6 PCI-E 2.0	No	3 Gbit/s, 4 Ports	Rev 2.0, 10 Ports	Yes	6.1 W
Q67	Cougar Point	SLH85(B2)	BD82Q67 (PCH)		LGA1155	DMI 2.0	4 GB/s	8 PCI-E 2.0	Yes	6 Gbit/s, 2 Ports & 3 Gbit/s, 4 Ports	Rev 2.0, 14 Ports	Yes	6.1 W
Q65	Cougar Point	SLH99(B2)	BD82Q65 (PCH)		LGA1155	DMI 2.0	4 GB/s	8 PCI-E 2.0	Yes	6 Gbit/s, 1 Port & 3 Gbit/s, 5 Ports	Rev 2.0, 14 Ports	Yes	6.1 W
B65	Cougar Point	SLH98(B2)	BD82B65 (PCH)		LGA1155	DMI 2.0	4 GB/s	8 PCI-E 2.0	Yes	6 Gbit/s, 1 Port & 3 Gbit/s, 5 Ports	Rev 2.0, 12 Ports	Yes	6.1 W
X68³	Patsburg		(PCH)	2011	LGA2011	DMI 2.0		x PCI-E 2.0		6 Gbit/s, ? Port & 3 Gbit/s, ? Ports	Rev 3.0, ? Ports	No

¹ X58 South Bridge is ICH10/ICH10R.
² X58 TDP includes the X58 IOH TDP in addition to the ICH10/ICH10R TDP.
³For Waimea Bay Highend Desktop Platform.

[edit]Core i Series Mobile chipsets

All Core i series mobile chipsets are integrated south bridge.

Chipset	Code Name	sSpec Number	Part numbers	Release Date	Processors	Process support	Bus Interface	Bus Speed	PCI Expresslanes	SATA	USB	TDP	FDI support
PM55	Ibex Peak-M	SLGWN(B2), SLH23(B3), SLGWP	BD82PM55 (PCH)^[24]	Sep 2009	Core i3/i5/i7 Mobile	45 nm, 32 nm	DMI	2 GB/s	8 PCI-E 2.0	3Gbit/s, 6 Ports	Rev 2.0, 14 Ports	3.5 W	No
HM55	Ibex Peak-M	SLGZS(B3)	BD82HM55 (PCH)^[25]	Jan 2010	Core i3/i5/i7 Mobile	45 nm, 32 nm	DMI	2 GB/s	6 PCI-E 2.0	3Gbit/s, 4 Ports	Rev 2.0, 12 Ports	3.5 W	Yes
HM57	Ibex Peak-M	SLGZR(B3)	BD82HM57 (PCH)^[26]	Jan 2010	Core i3/i5/i7 Mobile	45 nm, 32 nm	DMI	2 GB/s	8 PCI-E 2.0	3Gbit/s, 6 Ports	Rev 2.0, 14 Ports	3.5 W	Yes
QM57	Ibex Peak-M	SLGZQ(B3)	BD82QM57 (PCH)^[27]	Jan 2010	Core i3/i5/i7 Mobile	45 nm, 32 nm	DMI	2 GB/s	8 PCI-E 2.0	3Gbit/s, 6 Ports	Rev 2.0, 14 Ports	3.5 W	Yes
QS57	Ibex Peak-M	SLGZV(B3)	BD82QS57 (PCH)^[28]	Jan 2010	Core i3/i5/i7 Mobile	45 nm, 32 nm	DMI	2 GB/s	8 PCI-E 2.0	3Gbit/s, 6 Ports	Rev 2.0, 14 Ports	3.4 W	Yes
HM65	Cougar Point-M	SLH9D(B2) (Recalled) SLJ4P (B3)	BD82HM65 (PCH)^[29]	January 9, 2011	Core i3/i5/i7 Mobile	32 nm	DMI 2.0	4 GB/s	8 PCI-E 2.0	6 Gbit/s, 2 Ports & 3 Gbit/s, 4 Ports	Rev 2.0, 12 Ports	3.9 W	Yes
HM67	Cougar Point-M	SLH9C(B2) (Recalled) SLJ4N (B3)	BD82HM67 (PCH)^[30]	January 9, 2011	Core i3/i5/i7 Mobile	32 nm	DMI 2.0	4 GB/s	8 PCI-E 2.0	6 Gbit/s, 2 Ports & 3 Gbit/s, 4 Ports	Rev 2.0, 14 Ports	3.9 W	Yes
QM67	Cougar Point-M	SLH9B(B2)	BD82QM67 (PCH)^[31]		Core i3/i5/i7 Mobile	32 nm	DMI 2.0	4 GB/s	8 PCI-E 2.0	6 Gbit/s, 2 Ports & 3 Gbit/s, 4 Ports	Rev 2.0, 14 Ports	3.9 W	Yes
QS67	Cougar Point-M	SLHAG(B2)	BD82QS67 (PCH)^[32]		Core i3/i5/i7 Mobile	32 nm	DMI 2.0	4 GB/s	8 PCI-E 2.0	6 Gbit/s, 2 Ports & 3 Gbit/s, 4 Ports	Rev 2.0, 14 Ports	3.4 W	Yes

[edit]

AMD　ＣＰＵ＠　４０ｎｍ　２０１１Ｊａｎ
"Ontario" (40nm)

Model Number Step. CPU cores Freq. L2 Cache Multi ¹ Voltage Model GPU Config GPU GPU Freq. UMI TDP Socket Release Date Part Number(s)

C-30 B0 1 1.2 GHz 512 KB 6x 1.25 - 1.35 HD 6250 80:8:4 280MHz 2.5 GT/s 9 W BGA-413 January 4, 2011 CMC30AFPB12GT

C-50 B0 2 1.0 GHz 2x 512 KB 5x 1.05 - 1.35 HD 6250 80:8:4 280MHz 2.5 GT/s 9 W BGA-413 January 4, 2011 CMC50AFPB22GT

[edit]"Zacate" (40nm)

Model Number Step. CPU cores Freq. L2 Cache Multi ¹ Voltage Model GPU Config GPU GPU Freq. UMI TDP Socket Release Date Part Number(s)

E-240 B0 1 1.5 GHz 512 KB 7.5x 1.175 - 1.35 HD 6310 80:8:4 500MHz 2.5 GT/s 18 W BGA-413 January 4, 2011 EME240GBB12GT

E-350 B0 2 1.6 GHz 2x 512 KB 8x 1.25 - 1.35 HD 6310 80:8:4 500MHz 2.5 GT/s 18 W BGA-413 January 4, 2011 EME350GBB22GT

[edit]

All around the world

2011年2月23日

TSMC 28nm gate last gate first foundry 2010 2011

台積電28奈米大躍進

台積電法說會摘要(口語版)

2 意見:

IEDM 2009: HKMG gate-first vs gate-last options

[edit]Core i Series Mobile chipsets

"Ontario" (40nm)

[edit]"Zacate" (40nm)

[edit]

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