UMC's 28nm process technology is developed for applications that require the highest performance process technology. In October 2008, we were the first foundry to deliver fully functional 28nm SRAM chips, and have proven in silicon the high-K/metal solution that will be implemented on this technology node. UMC's 28nm progress was also recognized by the industry with the foundry being selected to present at the 2009 IEDM on a hybrid high-K/metal gate approach. Currently, we are already working with several customers to adopt their products on UMC's 28nm technology. 28nm Brochure (pdf, 339kb) 28nm Technology for Broad Applications
UMC incorporates a dual approach for its 28nm technology to address different market applications. Conventional silicon gate/silicon-oxy-nitride gate oxide technology is used for its LP (low power) process, which is ideal for portable applications such as mobile phone ICs. UMC's second option will utilize a high-k/metal gate stack for speed-intensive products such as graphic, application processor, and high-speed communication ICs. 
L28 Logic/MS(1) Devices
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Xilinx FPGAs go down to 28nmXilinx Inc. rolls out the first of its 7 series FPGAs with the shipment of the Kintex-7 K325T FPGA. This rollout marks the industry’s fastest product rollout of next generation PL devices built with 28nm technology, according to the company, which delivered the devices in less than 90 days from tapeout by leveraging TSMC’s 28nm HPL process.The Kintex-7 K325T device is the first FPGA in its class to deliver the highest number of channels per dollar at less than 12W of power for LTE wireless radio cards and next generation wireless base stations. Kintex-7 FPGAs claim to provide the optimized price performance required for FPDs, ultrasound equipment and many other applications and includes high-bandwidth, low jitter serial transceivers to address price sensitive wired communication applications. The FPGA is the first of 28 devices that make up the 7 series FPGA that includes the Artix-7 and Virtex-7 FPGA families. The Kintex-7 K325T FPGA contains the industry’s first 28nm Target Design Platform.Kintex-7 FPGAs are designed to provide price performance at the lowest power to meet requirements for key applications. The Kintex-7 FPGA family leverages the unified architecture shared across the 7 series of 28nm device families so customers can begin FPGA development now for designs that may later migrate to Artix-7 and Virtex-7 FPGAs.The devices are offered in conjunction with the Xilinx ISE Design Suite 13, AMBA 4 Advanced Extensible Interface (AXI) bus protocol-compliant IP, and targeted reference designs. All of these targeted design platform components run on the Kintex-7 FPGA KC705 evaluation board now being demonstrated for customers so that designers can evaluate the power consumption, performance, and capabilities of the new Kintex-7 K325T devices.Xilinx is also introducing the industry’s first 28nm Targeted Design Platform that combines the Kintex-7 K325T FPGA, ISE development tools, AXI 4 compliant IP, and an initial version of the base targeted reference design running on the Kintex-7 FPGA KC705 evaluation board.The 7 series targeted design platform allows customer to evaluate the features available in the Kintex-7 FPGA family including Artix-7 and Virtex-7 FPGAs. Designers and engineers have an easy to use, flexible FPGA platform as an alternative to inflexible and slow-to-develop ASIC or ASSP-based silicon solutions.Kintex-7 K325T FPGA initial samples are shipping now and order entry for the Kintex-7 FPGA base Targeted Design Platform that uses the Kintex-7 FPGA KC705 evaluation board will open in Q4 2011. The Virtex-7 485T FPGA and the 2 million logic cell 2000T will begin initial sampling in August and November of 2011, respectively. Artix-7 FPGA initial samples will ship first quarter of 2012.
Xilinx confirms: Samsung, TSMC in, UMC out at 28-nmDylan McGrath2/22/2010 5:00 PM ESTSAN FRANCISCO—Xilinx Inc. said Monday (Feb. 22) it will use leading foundry Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) as one of two foundry suppliers for its 28-nm FPGAs, a major strategy shift that has been the subject of industry rumors and analyst speculation for weeks.
Xilinx (San Jose, Calif.) said it is using TSMC and Samsung Electronics Co. Ltd.'s foundry division to make 28-nm parts, which are expected to begin sampling by the end of this year. Xilinx has long used a two foundry strategy at each process node. Samsung first joined Xilinx' foundry supplier roster at the 40-nm node, supplanting Toshiba. Xilinx' shift to TSMC is a bitter pill for rival foundry United Microelectronics Corp. (UMC), which has been a foundry supplier to Xilinx for more than a decade. Some analysts blamed 65-nm yield issues at UMC for a supply glitch that last summer materially impacted Xilinx sales, speculation which UMC later denied. UMC (Hsinchu, Taiwan) will presumabably continue to manufacture Xilinx parts at 65-nm, 40-nm and other nodes. Suresh Menon, product development vice president for Xilinx' programmable platforms development group, said Xilinx evaluates foundries' process technology at every process node in order to determine which suppliers to use.
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Suresh Menon
Xilinx Inc. |
"In this generation, as in every generation, we look at the needs for our next generation FPGAs and identify what process we need to deliver that generation of products," Menon said.
Xilinx is emphasizing power management in its 28-nm products (see related story). Menon said static power is a very significant portion of the total power dissipation of a chip at 28-nm. The choice of process technology at 28-nm is critical to achieving maximum power efficiency, he added. Menon said TSMC and Samsung offered Xilinx the best process technology options for high-performance, low-power process technology at 28-nm. Xilinx has been working with the two companies on 28-nm development for more than two years, he said. Some analysts, including Ian Ing of Broadpoint Amtech, have been saying for several weeks that Xilinx was expected to use TSMC at the 28-nm node. Altera Corp., the chief competitor to Xilinx in the programmable logic market, has used TSMC as its foundry supplier for years. Menon said the Xilinx-TSMC agreement would not restrict TSMC from working with Xilinx competitors. He noted that this is typical of TSMC's business practices and said TSMC manufacturers parts for competing suppliers in many markets, including graphics chips. Xilinx and Samsung last week announced that Spartan-6 FPGAs have achieved volume production on Samsung's 45-nm process.
UMC Takes Hybrid Approach to 28 nm High-k 2009-12-15 09:46:01
At IEDM, foundry UMC described a hybrid approach to high-k/metal gate deposition that seeks to take advantage of both the gate-first and gate-last approaches for 28 nm transistors. The hybrid scheme compares with a gate-last method supported by rival Taiwan foundry TSMC, and a gate-first approach by GlobalFoundries for the 28 nm generation.
At the International Electron Devices Meeting (IEDM) in Baltimore, United Microelectronics Corp. (UMC, Hsinchu, Taiwan) described a hybrid approach to high-k/metal gate deposition that seeks to take advantage of both the gate-first and gate-last approaches for 28 nm transistors. The UMC announcement of a hybrid approach for its 28 nm high-performance customers sets up an interesting competition at the 28 nm node, coming to market over the next year. Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan) will use a gate-last process flow for its high-performance 28 nm customers, while rival GlobalFoundries (Sunnyvale, Calif.) will stick with the gate-first approach developed by the members of the Fishkill Alliance for the 28 nm node, while considering the gate-last and gate-first approaches for the 22 nm generation, a spokesman said.
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Using a gate-last approach, UMC said the Ion-Ioff performance of the PFET achieved a ~30% enhancement over a gate-first approach. |
At IEDM, G.H. (Mike) Ma, a researcher at UMC's R&D center in Tainan, Taiwan, said the gate-first approach for PMOS transistors tends to result in a reduction (roll-off) of the flatband voltage as well as threshold voltage (Vt) levels exceeding 0.4 V, which he said are "unacceptable, certainly for high-performance applications." The flatband voltage (Vfb) roll-off is related to the thermal budget of the work-function metal, he said. The gate-last method, first developed by Intel Corp., resolves many of the performance issues, Ma said, but the approach is fairly expensive. The UMC hybrid approach "will not get to the performance level of the pure gate-last method," he said, but it is likely to be less expensive. The hybrid approach integrates "the high compatibility of the gate-first scheme for the NFET and the better thermal budget control of the gate-last scheme for the PFET." By using a gate-last approach for the PMOS transistor, and a gate-first approach for the NMOS transistor, UMC seeks to avoid "the high process complexity" of the pure gate-last approach, which Ma said remains "a challenging process." The hybrid process results in a "very good NMOS" transistor that has little of the mobility degradation seen in most high-k NMOS transistors, achieving 95% of the mobility with a SiON process flow. Ma said UMC achieved a low Vt of 0.25 V by optimizing the HfO2 dielectric, and by capping the TiN metal gate with a LaOx capping layer.
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The hybrid PMOS after ILD CMP (a), dummy poly removal (b), and low-resist metal CMP (c). (Source: UMC, IEDM 2009) |
On the PMOS side, the use of a gate-last approach delivers an Ion gain of 30% compared with the gate-first approach. UMC developed a diamond-shaped SiGe stress liner "which gives us an additional performance improvement," Ma said. Also, by doing annealing prior to high-k deposition, UMC avoids oxygen degradation of the high-k and interface layers, which supports high reliability, good TDDB, and relatively low levels of temperature-dependent reliability issues (NBTI and PBTI). "Due to the benefits of the low Vt, less interfacial layer oxide re-growth, and the strain boost from the gate-last approach, the Ion-Ioffperformance of the gate-last PFET achieved a ~30% enhancement," Ma concluded.
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聯電28nm製程SRAM試製成功 2008-10-28 15:39:01
聯電公司昨天宣佈，已經成功產出業界首顆全功能28nm製程SRAM芯片。在半導體業界，SRAM往往是試驗新製程工藝的首款產品。而28nm SRAM的試製成功也代表聯電基本擁有了28nm工藝的製造能力。
聯電的28nm SRAM基於該公司自行研發的LL低漏電製程工藝，採用雙重圖形曝光（double patterning）浸潤式微影和應變硅技術來製造。包含6個晶體管的SRAM尺寸為0.122平方微米。
聯電在應用28nm製程工藝時，會針對不同市場需求使用兩種不同的柵極技術。當製造諸如手機芯片等移動設備產品時，他們將採用自家低漏電製程，搭載傳統的硅柵極、氮氧化硅柵極氧化層技術，而當代工注重速度的產品注入GPU、應用處理器時，則會採用High-K金屬柵極技術。
聯電表示，使用公司現有的300mm晶圓工廠，28nm製程可帶來比40nm高近一倍的密度。同時他們還將在28nm平台上為客戶提供定制32nm工藝服務。
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