GlobalFoundries Tips 10nm Process
Foundry rolls FD-SOI, super-steep technology
Raising the ante in the foundry business, GlobalFoundries has added a 10nm finFET process to its roadmap and expanded its substrate offerings.
The foundry vendor plans to move into production with its 10nm finFET process in 2015, a year after its recently introduced 14nm finFET technology. In addition, the foundry vendor has also expanded its substrate offerings to five technologies: bulk planar, super-steep retrograde well (SSRW), fully depleted silicon-on-insulator (minimum), fully depleted silicon-on-insulator (maximum) and finFET.
Perhaps the biggest surprise on the roadmap is SSRW, a technology that controls short-channel effects using a doping technique. For SSRW, GlobalFoundries has been talking to SuVolta about the technology, according to multiple sources, but it’s unclear if the companies have reached a deal.
Ajit Manocha, chief executive of GlobalFoundries, disclosed the company’s new roadmap during a keynote presentation at the 2012 IEEE International Electron Devices Meeting (IEDM) in San Francisco on Tuesday. During the keynote, Manocha also addressed GlobalFoundries’ capacity plans, 450mm fabs and EUV. In fact, GlobalFoundries is not counting on EUV for the 10nm node.
His keynote was entitled, “Is the Fabless/Foundry Model Dead? We Don’t Think So. Long Live Foundry 2.0!” During the keynote, Manocha said the fabless/foundry model is alive and well in spite of recent comments from an undisclosed party. “Somebody said the foundry business is dead,” he said. “The same company wants to get into the foundry business. Something doesn’t add up.”
The comments may have been directed towards Intel. In a recent interview with SemiMD, Mark Bohr, senior fellow at Intel, said: “The traditional foundry model is running into problems. In order to survive, the foundries will have to become more like an integrated device manufacturer. Even some of the chief spokespeople for the foundries have said something similar. The foundry model worked well when traditional scaling was being followed and everybody knew where we were headed. In this era, where you continually have to invent new materials and new structures, it’s a lot tougher being a separate foundry and maskless design house. Being an IDM, we have design and process development under one roof. That’s really a significant advantage.”
At IEDM, Manocha agreed the foundries must act more like IDMs or virtual IDMs, saying the old model simply doesn’t work. “The traditional foundry model is that you work in isolation,” he said. “It doesn’t work.”
In the new model, dubbed Foundry 2.0, there is a deeper and earlier collaboration between foundries and their customers, he said. GlobalFoundries refers to its strategy as a “collaborative device manufacturer.”
As part of its strategy, GlobalFoundries continues to expand and accelerate its foundry offerings. Within its new 300mm fab in New York, the company has begun ramping the plant for 28nm and 20nm technology.
In 2013, the New York fab will be capable of running 30,000 wafers a month. At some point, the fab will capable of running 50,000 wafers a month.
Meanwhile, in September, GlobalFoundries rolled out its finFET technology for the 14nm node. GlobalFoundries is taking a “modular fin” approach with its bulk finFET offering, dubbed 14nm-XM. The 14nm-XM combines a 14nm-class fin with its 20nm back-end-of-line (BEOL) interconnect flow.
By taking the modular approach, the company has accelerated its process roadmap by a year. Early process design kits (PDKs) are available, with customer product tape-outs expected in 2013. Production, which is slated for 2014, will take place within GlobalFoundries’ new 300mm fab in New York.
Then, in October, rival Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) updated and accelerated its process roadmap. The world’s largest silicon foundry has accelerated its 16nm finFET efforts by one quarter and added a 10nm finFET technology to the roadmap. TSMC’s 10nm finFET process, dubbed CLN10FF, is expected to move into risk production close to the end of 2015.
GlobalFoundries moved to keep pace with TSMC. At IEDM, GlobalFoundries disclosed a 10nm finFET process, which is due out in 2015, or a year after 14nm finFET. “We have accelerated (the 10nm finFET process),” Manocha said after his keynote at IEDM.
At 10nm, GlobalFoundries and others may be forced to extend 193nm immersion, while also going with a multiple patterning scheme. EUV is late to the party and may miss the 10nm node. “10nm will be optical,” he said. “We have evidence that we can do 7nm with immersion.”
GlobalFoundries did not describe the details of its 10nm process. The foundry vendor did disclose it would offer several new technology platforms.
Besides planar bulk and finFETs, the company is moving to offer FD-SOI. In July, GlobalFoundries agreed to manufacture STMicroelectronics’ FD-SOI technology in both the 28nm and 20nm nodes. The SOI substrates are supplied by Soitec.
As part of its technology offerings, GlobalFoundries plans to offer two versions of FD-SOI: minimum and maximum. The maximum version is a technology tuned for a specific application. IBM and STMicroelectronics are examples of companies that would utilize maximum versions of FD-SOI.
The minimum version is a simple and an “out of the box” FD-SOI technology, said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries.
In addition, GlobalFoundries also plans to offer SSWR, a doping technology. “You add a ground plane below the channel,” Kengeri said. The technology is a 20nm planar process at 28nm costs. For years, several companies have been working on the technology to solve a major issue. A phenomenon called random dopant fluctuation (RDF) causes more than 70% of all random variations at 65nm and the problems are getting worse at each node.
To solve RDF and other problems, one company, SuVolta, recently rolled out a new transistor option that extends conventional bulk CMOS technology. SuVolta’s Deeply Depleted Channel (DDC) technology works by forming a deeply depleted channel when a voltage is applied to the gate.
In the distant future, GlobalFoundries is also looking at 450mm. It is part of the recently-announced Global 450 Consortium. The G450C group includes five IC manufacturers, with IBM and GlobalFoundries joining the original “International Sematech” members, Intel, Samsung, and TSMC. Those companies, along with Sematech and the SUNY-Albany College of Nanoscale Science and Engineering (CNSE), will sit on the board of directors that will govern the consortium.
The G450C demonstration line in Albany is targeted for 14nm design rules in early 2013. “Do I want to be the first one (on 450mm)? No. Do I want to be the last? No. I would like to be behind the first,” Manocha added.
The foundry vendor plans to move into production with its 10nm finFET process in 2015, a year after its recently introduced 14nm finFET technology. In addition, the foundry vendor has also expanded its substrate offerings to five technologies: bulk planar, super-steep retrograde well (SSRW), fully depleted silicon-on-insulator (minimum), fully depleted silicon-on-insulator (maximum) and finFET.
Perhaps the biggest surprise on the roadmap is SSRW, a technology that controls short-channel effects using a doping technique. For SSRW, GlobalFoundries has been talking to SuVolta about the technology, according to multiple sources, but it’s unclear if the companies have reached a deal.
Ajit Manocha, chief executive of GlobalFoundries, disclosed the company’s new roadmap during a keynote presentation at the 2012 IEEE International Electron Devices Meeting (IEDM) in San Francisco on Tuesday. During the keynote, Manocha also addressed GlobalFoundries’ capacity plans, 450mm fabs and EUV. In fact, GlobalFoundries is not counting on EUV for the 10nm node.
His keynote was entitled, “Is the Fabless/Foundry Model Dead? We Don’t Think So. Long Live Foundry 2.0!” During the keynote, Manocha said the fabless/foundry model is alive and well in spite of recent comments from an undisclosed party. “Somebody said the foundry business is dead,” he said. “The same company wants to get into the foundry business. Something doesn’t add up.”
The comments may have been directed towards Intel. In a recent interview with SemiMD, Mark Bohr, senior fellow at Intel, said: “The traditional foundry model is running into problems. In order to survive, the foundries will have to become more like an integrated device manufacturer. Even some of the chief spokespeople for the foundries have said something similar. The foundry model worked well when traditional scaling was being followed and everybody knew where we were headed. In this era, where you continually have to invent new materials and new structures, it’s a lot tougher being a separate foundry and maskless design house. Being an IDM, we have design and process development under one roof. That’s really a significant advantage.”
At IEDM, Manocha agreed the foundries must act more like IDMs or virtual IDMs, saying the old model simply doesn’t work. “The traditional foundry model is that you work in isolation,” he said. “It doesn’t work.”
In the new model, dubbed Foundry 2.0, there is a deeper and earlier collaboration between foundries and their customers, he said. GlobalFoundries refers to its strategy as a “collaborative device manufacturer.”
As part of its strategy, GlobalFoundries continues to expand and accelerate its foundry offerings. Within its new 300mm fab in New York, the company has begun ramping the plant for 28nm and 20nm technology.
In 2013, the New York fab will be capable of running 30,000 wafers a month. At some point, the fab will capable of running 50,000 wafers a month.
Meanwhile, in September, GlobalFoundries rolled out its finFET technology for the 14nm node. GlobalFoundries is taking a “modular fin” approach with its bulk finFET offering, dubbed 14nm-XM. The 14nm-XM combines a 14nm-class fin with its 20nm back-end-of-line (BEOL) interconnect flow.
By taking the modular approach, the company has accelerated its process roadmap by a year. Early process design kits (PDKs) are available, with customer product tape-outs expected in 2013. Production, which is slated for 2014, will take place within GlobalFoundries’ new 300mm fab in New York.
Then, in October, rival Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) updated and accelerated its process roadmap. The world’s largest silicon foundry has accelerated its 16nm finFET efforts by one quarter and added a 10nm finFET technology to the roadmap. TSMC’s 10nm finFET process, dubbed CLN10FF, is expected to move into risk production close to the end of 2015.
GlobalFoundries moved to keep pace with TSMC. At IEDM, GlobalFoundries disclosed a 10nm finFET process, which is due out in 2015, or a year after 14nm finFET. “We have accelerated (the 10nm finFET process),” Manocha said after his keynote at IEDM.
At 10nm, GlobalFoundries and others may be forced to extend 193nm immersion, while also going with a multiple patterning scheme. EUV is late to the party and may miss the 10nm node. “10nm will be optical,” he said. “We have evidence that we can do 7nm with immersion.”
GlobalFoundries did not describe the details of its 10nm process. The foundry vendor did disclose it would offer several new technology platforms.
Besides planar bulk and finFETs, the company is moving to offer FD-SOI. In July, GlobalFoundries agreed to manufacture STMicroelectronics’ FD-SOI technology in both the 28nm and 20nm nodes. The SOI substrates are supplied by Soitec.
As part of its technology offerings, GlobalFoundries plans to offer two versions of FD-SOI: minimum and maximum. The maximum version is a technology tuned for a specific application. IBM and STMicroelectronics are examples of companies that would utilize maximum versions of FD-SOI.
The minimum version is a simple and an “out of the box” FD-SOI technology, said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries.
In addition, GlobalFoundries also plans to offer SSWR, a doping technology. “You add a ground plane below the channel,” Kengeri said. The technology is a 20nm planar process at 28nm costs. For years, several companies have been working on the technology to solve a major issue. A phenomenon called random dopant fluctuation (RDF) causes more than 70% of all random variations at 65nm and the problems are getting worse at each node.
To solve RDF and other problems, one company, SuVolta, recently rolled out a new transistor option that extends conventional bulk CMOS technology. SuVolta’s Deeply Depleted Channel (DDC) technology works by forming a deeply depleted channel when a voltage is applied to the gate.
In the distant future, GlobalFoundries is also looking at 450mm. It is part of the recently-announced Global 450 Consortium. The G450C group includes five IC manufacturers, with IBM and GlobalFoundries joining the original “International Sematech” members, Intel, Samsung, and TSMC. Those companies, along with Sematech and the SUNY-Albany College of Nanoscale Science and Engineering (CNSE), will sit on the board of directors that will govern the consortium.
The G450C demonstration line in Albany is targeted for 14nm design rules in early 2013. “Do I want to be the first one (on 450mm)? No. Do I want to be the last? No. I would like to be behind the first,” Manocha added.
Mark LaPedus has covered the semiconductor industry since 1986, including five years in Asia when he was based in Taiwan. He has held senior editorial positions at Electronic News, EBN and Silicon Strategies. In Asia, he was a contributing writer for Byte Magazine. Most recently, he worked as the semiconductor editor at EE Times.
沒有留言:
張貼留言