TSMC Releases 16nm FinFET Design Flows 9/17/2013

TSMC Releases 16nm FinFET Design Flows

Leading pure-play foundry Taiwan Semiconductor Manufacturing Co. Ltd. has announced the existence of three reference design flows for FinFET and 3D-stacked ICs that have been taken to silicon. The silicon validation of these flows signifies the opening up of the manufacturing processes for the design of production volume chips.
Intel was the pioneer of the FinFET in commercial production and remains the only company with such a manufacturing process. However, TSMC is reported to have signed to supply Apple with processors on a three-year contract that will include some FinFET production (see TSMC signs up Apple for three-year FinFET deal).
The three TSMC design flows are: a digital design flow for TSMC's 16FinFET process; a custom design flow for 16FinFET that offers transistor-level design of analog, digital, mixed-signal, custom digital and memory; and a 3D-IC flow for the design of vertically stacked structures and multi-die assemblies.
EDA software vendors collaborated with TSMC to develop and validate these design routes using silicon test vehicles, TSMC said in a press release. However, TSMC did not indicate which companies' tools had been proved effective at which stages of the design process.
The 16FinFET digital design flow uses the Cortex-A15 multicore processor, licensed from ARM Holdings plc, as its validation vehicle for certification. It helps designers adopt the FinFET by addressing such issues as RC modeling, power-performance-area trade-offs, low-vdd operation, electromigration, and power management.
Integrating multiple components in a single stacked component can provide benefits in terms of physical scaling and power consumption. TSMC's 3D-IC design flow addresses such items as through-transistor-stacking (TTS) technology; through silicon vias (TSVs) plus microbumps, back-side metal routing; and TSV-to-TSV coupling extraction.
"These reference flows give designers immediate access to TSMC's 16FinFET technology and pave the way to 3D-IC Through-Transistor-Stacking (TTS) technology," said Cliff Hou, vice president of R&D at TSMC.

TSMC and OIP Ecosystem Partners Deliver 16FinFET and 3D IC Reference Flows http://www.tsmc.com
Issued by: TSMC
Issued on: 2013/09/17
Hsinchu, Taiwan, R.O.C. – Sept. 17, 2013 – TSMC (TWSE: 2330, NYSE: TSM) today released three silicon-validated Reference Flows within the Open Innovation Platform® (OIP) that enable 16FinFET systems-on-chip (SoC) designs and 3D chip stacking packages. Leading Electronic Design Automation (EDA) vendors collaborated with TSMC to develop and validate all these flows through multiple silicon test vehicles.The new Reference Flows are: 1. TSMC’s 16FinFET Digital Reference Flow, providing comprehensive technology support to address post-planar design challenges including extraction, quantized pitch placement, low-vdd operation, electromigration, and power management. 2. The 16FinFET Custom Design Reference Flow, offering full custom transistor-level design and verification including analog, mixed-signal, custom digital and memory. 3. The 3D IC Reference Flow, addressing emerging vertical integration challenges with true 3D stacking.
“These Reference Flows give designers immediate access to TSMC’s 16FinFET technology and pave the way to 3D IC Through-Transistor-Stacking (TTS) technology,” said TSMC Vice President of R&D, Dr. Cliff Hou. “Delivering our most advanced silicon and manufacturing technologies as early and completely as possible to our customers is a major milestone for TSMC and its OIP design ecosystem partners.”
16FinFET Digital Reference Flow
The 16FinFET Digital Reference Flow uses the ARM Cortex™-A15 multicore processor as a validation vehicle for certification. It helps designers adopt the new technology by addressing FinFET structure related challenges of complex 3D Resistance Capacitance (RC) modeling and quantized device width. In addition, the flow provides methodologies for boosting power, performance and area (PPA) in 16nm, including low-voltage operation analysis, high-resistance layer routing optimization for interconnect resistance minimization, Path-Based Analysis and Graph-Based Analysis correlation to improve timing closure in Automatic Place and Route (APR).
16FinFET Custom Design Reference Flow
The 16FinFET Custom Design Reference Flow enables custom design by addressing the growing complexity of 16FinFET process effects and provides methodologies for design compliance in 16nm manufacturing and reliability.
3D IC Reference Flow
The 3D IC process produces significant silicon scaling, power and performance benefits by integrating multiple components on a single device. TSMC’s 3D IC Reference Flow addresses emerging integration challenges through 3D stacking. Key features include Through-Transistor-Stacking (TTS) technology; Through Silicon Via (TSV)/microbump and back-side metal routing; TSV-to-TSV coupling extraction.
About Open Innovation Platform
OIP promotes innovation for the semiconductor design community and ecosystem partners based on TSMC’s complete technology portfolio. OIP includes a set of ecosystem interfaces and collaborative components initiated and supported by TSMC that efficiently empower innovation throughout the supply chain, enabling the sharing of newly created revenue and profitability. OIP initiatives include reference flows, third-party IP validation, TSMC library IP, design kits and an online design portal.
About TSMC
TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry segment’s largest portfolio of process-proven libraries, IPs, design tools and reference flows. The Company’s owned capacity in 2013 is expected to be about 16.5 million (8-inch equivalent) wafers, including capacity from three advanced 12-inch GIGAFAB™ facilities, four eight-inch fabs, one six-inch fab, as well as TSMC’s wholly owned subsidiaries, WaferTech and TSMC China. TSMC is the first foundry to provide 28-nanometer production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please visit http://www.tsmc.com.

發佈單位 : 台灣積體電路製造股份有限公司
發佈日期 : 2013/09/17
台積公司今(17)日宣佈,在開放創新平台(Open Innovation Platform®, OIP)架構下成功推出三套全新經過矽晶驗證的參考流程,協助客戶實現16FinFET系統單晶片(SoC)與三維晶片堆疊封裝設計,電子設計自動化領導廠商與台積公司已透過多種晶片測試載具合作開發並完成這些參考流程的驗證。台積公司全新的參考流程如下:(一)16FinFET數位參考流程提供完整的技術支援協助解決後平面式(Post-Planar)晶片設計的挑戰,包括粹取(Extraction)、量化線距佈局(Quantized Pitch Placement)、低VDD電壓操作、電遷移、以及電源管理;(二)16FinFET客製化設計參考流程提供包括類比、混合信號、客製化數位與記憶體等電晶體級客製化設計與驗證;(三)三維積體電路(3D IC)參考流程能夠克服以三維堆疊方式進行垂直整合時所帶來的新挑戰。
台積公司研究發展副總經理侯永清博士表示:「這些參考流程讓設計人員能夠立即採用台積公司的16FinFET製程技術進行設計,並且為發展穿透電晶體堆疊(Through Transistor Stacking, TTS)技術的三維積體電路鋪路。對於台積公司及其開放創新平台設計生態環境夥伴而言,及早並完整地提供客戶先進的矽晶片與生產技術著實是一項重大的里程碑。」
16FinFET數位參考流程使用ARM CortexTM-A15多核心處理器做為驗證載具,協助設計人員採用此項新技術克服與FinFET結構相關的挑戰,包括複雜的三維電阻電容模型(3D RC Modeling)與量化元件寬度(Quantized Device Width)。此參考流程亦提供改善16奈米製程功耗、效能與面積的方法,包括低電壓操作分析、高電阻層繞線最佳化以便將電路電阻降到最低、以及針對以路徑與繪圖為基礎的分析(Path-Based Analysis and Graphic-Based Analysis)進行比對以改善自動佈局繞線(Automatic Place and Route, APR)的時序收斂(Timing Closure)。
三維積體電路製程藉由整合多個晶片於同一系統上以顯著提升在尺寸微縮、功耗與效能方面的優勢,台積公司提供的三維積體電路參考流程能夠解決以三維堆疊方式進行垂直整合時所帶來的新挑戰,其主要特性包括穿透電晶體堆疊技術、矽穿孔(Through Silicon Via, TSV)/微凸塊及背面金屬繞線(Microbump and Back-side Metal Routing)、以及矽穿孔對矽穿孔耦合粹取(TSV-to-TSV Coupling Extraction)。
台積公司 (TSMC) 是全球最大的專業積體電路製造服務公司,提供業界卓越的製程技術、元件資料庫、設計參考流程及其他先進的晶圓製造服務。台積公司預計2013年將擁有足以生產相當於1,650萬片八吋晶圓的產能,其中包括三座先進的GIGAFAB™ 十二吋晶圓廠 (晶圓十二廠、晶圓十四廠及晶圓十五廠)、四座八吋晶圓廠 (晶圓三、五、六及八廠)、一座六吋晶圓廠(晶圓二廠)。此外,台積公司亦有來自其轉投資子公司美國WaferTech公司以及台積電(中國)有限公司充沛的產能支持。台積公司係首家使用28奈米製程技術為客戶成功試產晶片的專業積體電路服務公司。其企業總部位於臺灣新竹。進一步資訊請至台積公司網站www.tsmc.com.tw查詢。